Deliverables
Work Package 1
- D1.1 Project manual including Quality Assurance guidelines
- D1.4 Project Progress Report 1
- D1.4 Project Progress Report 2
- D1.5 Project Progress Report 3
- D1.6 Final Project Report
- D1.7 Minutes from meetings
Work Package 2
- D2.1 Project manual including Quality Assurance guidelines
- D2.2 System specification document
Work Package 3
- D3.1 Cell library requirements for microcontroller synthesis
- D3.2 Rad-hard library design
- D3.3 Memory and ADC/DAC library requirements
- D3.4 Memory and ADC/DAC library design
Work Package 4
- D4.1 Preliminary test chip for analog components
- D4.2 Report on microcontroller chip design and production
Work Package 5
- D5.1 Binary utilities (binutils)
- D5.2 CompCert C compiler for Peaktop
Work Package 6
- D6.1 Preliminary RTSK on target hardware
- D6.2 Final RTSK on target hardware
- D6.3 Drivers, libraries and tools
Work Package 7
- D7.1 Test report of the preliminary test chip
- D7.2 Packaged MORAL chips
- D7.3 MORAL chip test report
- D7.4 Stress test PCBs
- D7.5 Stress test report
- D7.6 Complete MORAL chip microcontroller datasheet
Work Package 8
- D8.1 MORAL demonstrator specification
- D8.2 Manufactured and assembled PCB
- D8.3 Demonstrator test report
Work Package 9
- D9.1 Preliminary exploitation plan
- D9.2 Business plan
- D9.3 Registration number of the NewEuCo
- D9.4 Final exploitation plan
- D9.5 Balance sheet for the first year of the new European company
Work Package 10
- D10.2 Project website
- D10.3 Dissemination report 1
- D10.4 Dissemination report 2
- D10.5 Dissemination report 3